1. Technical Field
The present invention generally relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device having a silicide layer on a gate electrode and a manufacturing method thereof.
2. Background Art
For improved miniaturization, density, and speed of semiconductor elements such as MOS (Metal Oxide Semiconductor) transistors and for reduced power consumption thereof, it is important to reduce resistances of polysilicon gate electrodes, polysilicon wirings, and source/drain diffusion layers of MOS transistors. A silicide process which uses silicide, a compound of silicon and metal, is known as a technology for reducing these resistances.
When a silicide process is used to form MOS transistors, a silicide layer is formed in the surface portion of polysilicon gate electrodes and the surface portion of source/drain regions. Since the silicide layer has a lower resistance than that of polysilicon, resistances of the gate electrodes and the source/drain regions are reduced by the silicide process. A salicide process, a method for siliciding a gate electrode and source/drain regions simultaneously in a self-aligned manner, is also known in the art.
FIG. 11 is a cross-sectional view of a MOS transistor formed by a conventional salicide process (for example, Japanese Laid-Open Patent Publication No. 2003-224265). As shown in FIG. 11, the conventional semiconductor device has a gate electrode 231, a sidewall 210, and source/drain regions 237. The gate electrode 231 has a rectangular cross section and is formed on a substrate 201 with a gate insulating film 202 interposed therebetween. The sidewall 210 is formed on the substrate 201 and covers the whole side surface of the gate electrode 231. The source/drain regions 237 are formed in the surface portion of the substrate 201 on both sides of the gate electrode 231. The gate electrode 231 is formed from polysilicon or the like. A silicide layer 214 of a refractory metal is formed in the surface portion of the gate electrode 231 and the respective surface portions of the source/drain regions 237.
Since the sidewall 210 is formed on the side surface of the gate electrode 231, such a semiconductor device can be produced by a salicide process. In the salicide process, a refractory metal film (not shown) is formed on the substrate 201 so as to cover the gate electrode 231 and the sidewall 210 formed on the side surface of the gate electrode 231. The surface portion of the gate electrode 231 and the respective surface portions of the source/drain regions 237 are then silicided in a self-aligned manner by heat treatment. Note that a cap film which serves as an anti-oxidation film is also formed on the refractory metal film.
In such a semiconductor device, the gate electrode 231 has a rectangular cross section, and the sidewall 210 covers the whole side surface of the gate electrode 231. Therefore, film stresses are generated in the boundary between the surface of the gate electrode 231 and the sidewall 210 when the refractory metal and silicon are caused to react by heat treatment in the silicidation process. Such film stresses are applied intensively to the corners of the top surface of the gate electrode 231. As a result, silicide is likely to gather in the middle of the surface portion of the gate electrode 231, and both ends of the gate electrode 231 are less likely to be silicided. As shown in FIG. 11, the silicide layer 214 formed in the surface portion of the gate electrode 231 is therefore likely to be shallow at the ends and deep in the middle when viewed in cross section. The reason why the silicide layer 214 has such an uneven thickness is as follows: refractory metal expands to a large degree by heat treatment, whereas silicon does not expand very much. Moreover, the sidewall 210 which is formed from a silicon oxide film, a silicon nitride film, a lamination thereof, or the like is less likely to expand by heat treatment as compared to silicon. Therefore, high film stresses are generated especially near the boundary between silicon and the sidewall and the refractory metal in the upper portion of the gate electrode 231.
Forming a silicide layer 214 having a large cross-sectional area in the gate electrode 231 can reduce the resistance of the gate electrode 231. In the above semiconductor device, however, both ends of the gate electrode 231 are less likely to be silicided, and therefore, it is difficult to form a silicide layer 214 having a uniform thickness and a large cross-sectional area in the gate electrode 231. Accordingly, the gate electrode 231 has an increased, unstable resistance, causing delay of electric signals of the gate electrode 231 and unstable operation of the semiconductor device. Especially, as the gate width of the gate electrode 231 is reduced, the influence of the corners (ends) of the top surface of the gate electrode 231 is increased, whereby the rate of increase in resistance of the gate electrode 231 and the incidence of delay of electric signals are increased. As a result, operation of the semiconductor device becomes more unstable. Such a problem occurs when the width of the gate electrode is 150 nm or less, and becomes significant when the width of the gate electrode is 100 nm or less.
Japanese Laid-Open Patent Publication No. 9-74199 proposes a method for increasing the cross-sectional area of a silicide layer. As shown in FIG. 12, in this method, the height of sidewalls 7a, 7b is reduced so that each silicide layer 9a, 9b includes a part of a side surface of a corresponding gate electrode 4a, 4b. In this structure, however, a substrate 1 which forms source/drain regions 9c may be damaged in the step of forming the sidewalls 7a, 7b, whereby a junction leakage current may be increased. Moreover, control of the sidewall width may become difficult due to the reduced height of the sidewalls 7a, 7b. 
Japanese Laid-Open Patent Publication No. 7-66421 proposes another method for increasing the cross-sectional area of a silicide layer. As shown in FIG. 13, in this method, the corners (ends) of the top surface of a gate electrode 21 are removed so that a silicide layer 31 has a mountain shape. In this method, however, the top surface of the gate electrode 21 has sharp portions (corners), and film stresses which are generated between the top surface of the gate electrode 21 and a refractory metal layer are applied intensively to these sharp portions. As a result, in heat treatment, a cap film and the refractory metal film may crack and thermal diffusion of the refractory metal into silicon may be prevented. The resultant silicide layer therefore may not have a sufficient thickness.